Notes:

DLC/SXL chips work with BARB method. DRAM.exe from Cyrix.exe tool is helpful for setting memory refresh >15ns, allowing for improved performance. ~40ns is (seemingly) optimal. J37 being short and changing J35 are not required for 40MHz FSB operation. J37 seems to slow the board slightly. The board works fine with 15ns cache at 40MHz, even though 12ns is "required" by the manual.

The manual also does not document/improperly documents the TAG situation. MTL says nothing is needed at U38 for 64k L2. This isn't true. One 64kx1 chip is needed, as noted in the manual.