| Microarchitecture | |
|---|---|
| Core | Sunny Cove |
| L2 Cache | 512KB per core |
| L3 Cache | 3 MB per slice (24 MB total) |
| Bus Speed | Unknown |
| Frequency | Unknown |
| Core count | 2 |
| Multiplier | Unknown |
| AVX Support | AVX-512, AVX VNNI |
| Thread count | 2 |
| Instruction set | x86-64 |
| Inference Compute Engine | |
|---|---|
| ICE count | 12 |
| Vector DSP | Cadence Tensilica Vision P6, 512-bit VLIW |
| TCM per ICE | 256 KB |
| DL precision | INT8, INT4, INT2, INT1, FP16 |
| MACs per ICE | 4096 |
| TCM bandwidth | 68 TB/s total |
| Deep SRAM per ICE | 4 MB |
| Memory | |
|---|---|
| LLC total | 24 MB (3 MB per slice, 8 slices) |
| TCM total | 3 MB |
| Main memory | LPDDR4x-4266 |
| Deep SRAM total | 48 MB |
| Memory capacity | 16/32GB |
| Memory bandwidth | 67.2GB/s |
| Fabrication | |
|---|---|
| Process | Intel 10 nm |
| Die size | 239 mm² |
| Transistor count | 8.5 billion |
| Power | |
|---|---|
| TDP | 12W |
| Voltage | Unknown |
| Form Factor | |
|---|---|
| Type | M.2 Key M |
| Interface | PCIe Gen3 x4 |
The Intel Nervana NNP-I 1150 (Spring Hill, SRK1U) is an M.2 Key M form factor inference accelerator. It integrates two Intel Sunny Cove cores and twelve Inference Compute Engines (ICEs) on a 10nm SoC. The chip includes 24 MB of shared LLC, 3 MB of tightly coupled memory (256 KB per ICE), and 48 MB of deep SRAM (4 MB per ICE). It supports LPDDR4x-4266 memory with 16 or 32 GB capacity and 67.2 GB/s bandwidth.
The card connects via M.2 PCIe Gen3 x4 and has a typical TDP of 12W. It is designed to accelerate low-latency AI inference workloads and operates independently with an embedded Linux-based OS loaded by the host driver at runtime.
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