Instruction sets
(most recent first)
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Instruction set#25(Extended MMX) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#9(SSE) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#10(SSE2) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#17(SSE3) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#18(SSSE3) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#19(SSE4.1) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#48(AES) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#20(NX Bit) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#24(VT-x/AMD-V) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#50(SHA) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin -
Instruction set#35(VIA Padlock) has been associated toChip family#476(VIA Nano X2 (Isaiah)) by Fouquin
Chip families
(most recent first)
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Chip family#476(VIA Nano X2 (Isaiah)) has been associated toChip family#431(VIA Nano Quad (Isaiah II)) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toChip family#135(VIA Eden) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toChip family#68(VIA C7 (Esther)) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toChip family#475(VIA Nano (Isaiah)) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toCPU socket#42(NanoBGA2) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#35(VIA Padlock) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#50(SHA) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#24(VT-x/AMD-V) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#20(NX Bit) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#48(AES) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#19(SSE4.1) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#18(SSSE3) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#17(SSE3) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#10(SSE2) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#9(SSE) by Fouquin -
Chip family#476(VIA Nano X2 (Isaiah)) has been associated toInstruction set#25(Extended MMX) by Fouquin -
Chip family#476has been inserted by FouquinAttribute Old value New value idnull 476 miscSpecsnull Die Size: 66 mm²<br/>Foundry: TSMC<br/>L1 Cache: 128 KB (per core)<br/>L2 C... namenull VIA Nano X2 (Isaiah)