Logs - TRW

Logs

5 operation(s)

Chip family#73 has been updated by app:ppt-to-json

Sep 11, 2024, 6:28:45 PM UTC

Attribute	Old value	New value
`miscSpecs`		Microarchitecture: CPUID: <br/>L1 cache: 8KB code, unknown data<br/>Process...

f8b047ff41dfc1654c6e46c95ec1a1210d3ca3ef

Sep 11, 2024, 6:28:45 PM UTC

Chip family#73 (STPC Atlas) has been associated to Entity documentation#120 (STPC Atlas datasheet [2002-07-24]) by CarlosS.M.

May 23, 2024, 7:11:21 PM UTC

557dac79b75556574ae2e3e7e3a0e07796a34edb

May 23, 2024, 7:11:21 PM UTC
Chip family#73 (STPC Atlas) has been associated to Instruction set#4 (i486) by CarlosS.M.

May 23, 2024, 6:58:35 PM UTC

5472fbc76118a5291cf9a39ca4269c6d1fa4c55d

May 23, 2024, 6:58:35 PM UTC
Chip family#73 (STPC Atlas) has been associated to RAM type#4 (SDR UDIMM) by CarlosS.M.

May 23, 2024, 6:58:35 PM UTC

5472fbc76118a5291cf9a39ca4269c6d1fa4c55d

May 23, 2024, 6:58:35 PM UTC

Chip family#73 has been updated by CarlosS.M.

May 23, 2024, 6:58:35 PM UTC

Attribute	Old value	New value
`L1code`	null	8KB

5472fbc76118a5291cf9a39ca4269c6d1fa4c55d

May 23, 2024, 6:58:35 PM UTC