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Chip family#194has been updated by Wolt1xAttribute Old value New value miscSpecsMicroarchitecture: CPUID: <br/>L1 cache: 32KB code, 32KB data<br/>Process n... Microarchitecture: CPUID: <br/>L1 cache: 32KB code, 32KB data<br/>Process n... -
Chip family#194has been updated by app:ppt-to-jsonAttribute Old value New value miscSpecsMicroarchitecture: CPUID: <br/>L1 cache: 32KB code, 32KB data<br/>Process n... -
Chip family#194(Celeron M (Penryn)) has been associated toEntity documentation#200(Intel Celeron Processor ULV 763 Export Compliance Metrics []) by Wolt1x -
Chip family#194(Celeron M (Penryn)) has been associated toEntity documentation#199(Intel Celeron M Processor ULV 700 Series Export Compliance Metrics []) by Wolt1x -
Chip family#194(Celeron M (Penryn)) has been associated toInstruction set#20(NX Bit) by computerguy096 -
Chip family#194(Celeron M (Penryn)) has been associated toInstruction set#11(AMD64/EM64T) by computerguy096 -
Chip family#194(Celeron M (Penryn)) has been associated toInstruction set#18(SSSE3) by computerguy096 -
Chip family#194(Celeron M (Penryn)) has been associated toInstruction set#6(i686) by computerguy096 -
Chip family#194has been inserted by computerguy096Attribute Old value New value L1codenull 32KB L1codeRationull 1 L1datanull 32KB L1dataRationull 1 idnull 194 namenull Celeron M (Penryn) processNodenull 45