Overview

The VL82C520 Lynx/M chipset is VLSI's system solution optimized for the expanding mobile Pentium market. Carrying forward VLSI's mobile strategy and leveraging successful desktop innovations to offer a complete solution, Lynx/M leaps forward and integrates the system controller into a single Ball Grid Array (BGA) package. Included in the Lynx/M solution is a PCI "Super I/O" controller that integrates all the standard mobile peripherals. The Lynx/M offers a total solution compatible with the Common Architecture industry standard implementing highly efficient DDMA (Distributed DMA), Serial IRQ, and features for primary PCI hot docking using a Common Architecture compatible PCI to PCI bridge in the docking station.

Background:

Lynx/M incorporates functions from previous desktop and mobile chipsets. Baselinning from proven core system blocks and modifying to reflect new market requirements allows VLSI to meet the Time-To-Market expectations while minimizing risk.

Utilizing high-pin count BGA packaging allows Lynx/M to reduce board space requirements by greater than 45%. this allows room on the PCB for additional functionality while reducing the complexity of multi-layer system boards.

Accessing VLSI's internal fab technology allows Lynx/M a path to an advanced 0.6um CMOS process thereby achieving a true 3.3V system without performance trade-offs.

Features:

• Support for Pentium and Pentium-class CPUs
• 64-bit wide SDRAM, EDO, and FPM DRAM controller
• Nine-deep, 64-bit fast-access smart write buffers
• Fully PCI 2.1 compliant, 33MHz, synchronous or asynchronous, high performance (120 MB/s) PCI bus with full concurrency to support high bandwidth multi-media
• Flexible L2 write-back cache controller supporting 3-1-1-1-1-1-1-1 burst cycles
• Highly integrated chipset in low-profile BGA packages
• Active thermal feedback (ATF) for closed-loop thermal control of the CPU
• PCI bridge support for high-performance primary PCI hot docking
• Common Architecture Serial Bus minimizes docking connector pin count
• SMB/I2C system management bus improves battery monitoring
• Singular ROM for keyboard, System and graphics BIOS
• Full 2 channel Bus Mastering IDE controller
• Integrated '077 FDC
• Two 16550 UARTs
• 8052 keyboard controller with built-in scan for matrix keyboards and boot controller functionality
• system clocks from power-managed PLLs with on-board buffering for distribution
• Two PWMs to provide LCD backlight and contrast control
• Parallel port with PS2, EPP and ECP extensions
• Built-in IrDA 1.1 Fast Infrared communications port
• Multiple VCC rails and on-board level shifters to provide inderpendent power-down and true 5.0 Vdc peripheral support
• Support for three PS2 ports
• Real-Time Clock with CMOS
• 25 GPIO pins with expansion
• Built-in Sub-ISA bus for 16-bit DMA ISA Master audio device
• Supports 3.3V and 0V suspend with multiple resume events, I/O trapping, and audio 0V suspend/resume
• Bus Keeper I/Os to reduce battery drain in suspend mode
• Supports shut-down option for CPU core power during powered suspend to maximize battery life
• Supports CPU clock division emulation to effectively reduce CPU clock frequency
• Plug-N-Play support
• Compliant with Microsoft recommendations for Win '95