Overview

The 82093AA IOAPIC is designed for multi-processor interrupt management and provides both static and dynamic symmetric interrupt distribution across all processors. It comes in a 64-pin PQFP package and features an X-Bus interface.

Key Features:

• Multiprocessor Interrupt Management
• Dynamic Interrupt Distribution
  • Routing interrupt to the lowest priority processor
• Software Programmable Control of Interrupt Inputs
• Offloads interrupt-related traffic from the memory bus
• 24 Programmable Interrupts:
  • 13 ISA Interrupts supported
  • 4 PCI Interrupts
  • 1 Interrupt/SMI# Rerouting
  • 2 Motherboard Interrupts
  • 1 Interrupt used for INTR Input
  • 3 General Purpose Interrupts
• Independently programmable Edge/Level Sensitivity Interrupts
  • Each interrupt can be programmed to respond to active high or low inputs
• X-Bus Interface:
  • CS for flexible decode of the IOAPIC device
  • Index Register Interface for optimum memory usage
  • Registers are 32-bit wide to match the PCI to Host Bridge Architecture
• 2-register memory space is relocatable for increased system flexibility when assigning memory space usage