• HMC HM6818A
• Samsung KS82C6818A
• ALi M5818
• ALi M5818P
• Motorola MC146818A
• Motorola MCCS146818BF
• Winbond W85C168
• Winbond W85C178

Main difference between variants:

• 6818A (this one): pin 1 is MOT (bus type), pin 16 is STBY
• 6818: pin 1 and 16 are not connected (unused)
• W85C178: 6818A compatible with 114 bytes of non voltatile storage

From Mototrola datasheet:

The MC146818A Real-Time Clock plus RAM is a peripheral device which includes the unique MOTEL concept for use with various microprocessors, microcomputers, and larger computers. This part combines three unique features: a complete time-of-day clock with alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static RAM. The MC146818AFN uses high-speed CMOS technology to interface with 1MHz processor busses, while consuming very little power.

The Real-Time Clock plus RAM has two distinct uses. First, it is designed as a battery powered CMOS part (in an otherwise NMOS/TTL system) including all the common battery backed-up functions such as RAM, time, and calendar. Secondly, the MC146818A may be used with a CMOS microprocessor to relieve the software of the timekeeping workload and to extend the available RAM of an MPU such as the MC146805E2

Features:

• Low-Power, High-Speed, High-Density CMOS
• Internal Time Base and Oscillator
• Counts Seconds, Minutes, and Hours of the Day
• Counts Days of the Week, Date, Month, and Year
• 3 V to 6 V Operation
• Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
• Time Base Oscillator for Parallel Resonant Crystals
• 40 to 200 uW Typical Operating Power at Low Frequency Time Base
• 4.0 to 20 mW Typical Operating Power at High Frequency Time Base
• Binary or BCD Representation of Time, Calendar, and Alarm
• 12- or 24-Hour Clock with AM and PM in 12-Hour Mode
• Daylight Savings Time Option
• Automatic End of Month Recognition
• Automatic Leap Year Compensation
• Microprocessor Bus Compatible
• Selectable Between Motorola and Competitor Bus Timing
• Multiplexed Bus for Pin Efficiency
• Interfaced with Software as 64 RAM Locations
• 14 Bytes of Clock and Control Registers
• 50 Bytes of General Purpose RAM
• Status Bit Indicates Data Integrity
• Bus Compatible Interrupt Signals (IRQ)
• Three Interrupts are Separately Software Maskable and Testable
  • Time-of-Day Alarm, Once-per-Second to Once-per-Day
  • Periodic Rates from 30.5 us to 500 ms
  • End-of-Clock Update Cycle
• Programmable Square-Wave Output Signal
• Clock Output May Be Used as Microprocessor Clock Input
  • At Time Base Frequency /1 or /4