Sun STP2003QFP (PCI I/O Controller)
dateType
Chipset part
datePCI Vendor ID
108E
datePCI Device ID
1000 1001
No additional chip specs

Description:

STP2003 PCIO

The PCIO chip is a high integration, high performance single chip IO subsystem connected to the PCI local bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic slave DMA bus (pseudo-ISA bus) to which off-the-shelf peripherals are connected to implement the rest of the Sun core IO system.

PCIO is built around an internal bus (the Channel Engine Interface). This structure is the key to the PCIOs modularity. Above the Channel Engine Interface, the Bus Adapter connects to the PCI bus. The two identical ports on the Channel Engine Interface are used for each of PCIO’s functional units: Ethernet and EBus2. Each of these has its own set of control and status registers, data buffers and the core logic function.

PCI Function 0: Sun EBus2 IO Bridge
Vendor ID: 108E
Device ID: 1000

PCI Function 1: Sun Happy Meal 10/100 Ethernet Controller
Vendor ID: 108E
Device ID: 1001

Features

  • PCI Local Bus master/slave interface, compliant with PCI Local Bus Specification, Revision 2.1 [1].
  • 10baseT (802.3) and 100baseT (802.30) Ethernet, using a derivative of Media Access Control (MAC), with fully buffered transmit and receive channels; media-independent interface (MII).
  • Expansion bus interface (EBus2), supporting eight external devices and four buffered slave DMA channels.
  • Oscillator for 40 MHz SCSI clock, and free running 10 MHz real-time clock.
  • IEEE 1149.1 JTAG compliant test architecture.

The following functions are implemented with off-the-shelf devices, connecting directly to the EBus2:

  • PC87303 Super IO, integrating 82077-compatible floppy controller with DMA, parallel port, P1284-compliant, with ECP and EPP with DMA and two 16C550 serial controllers with 16-byte FIFOs for keyboard and mouse.
  • Two high performance sync/async serial ports, using Siemens SAB82532, 460.8 KBaud async, 384 KBaud sync.
  • Sun compatible NVRAM, MK48T59, with alarm clock interrupt for power management.
  • EPROM of flash EPROM, 8-bit wide, up to 16 Mbyte, for OBP and POST code.
  • CS4231 Audio CODEC.
  • Access to USC and DSC control port.
  • Auxiliary IO ports, for power supply control, temperature sensor, frequency calibration and other miscellaneous functions.
Last updated 2024-01-23T21:02:04Z
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