Sun SME2411 (UltraSPARC-IIi APB)
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SME2411 APB

The Advanced PCI Bridge (APBTM), SME2411, is a PCI-to-PCI bridge chip that is compatible with version 2.1 of the PCI Local Bus Specification [1]. The APB features a connection path between a 32-bit bus running at speeds up to 66 MHz on the primary interface and two 32-bit, 5 V or 3.3 V, PCI buses (each running up to 33 MHz), on the secondary interface. It is primarily intended as an interconnect mechanism, for use in an UltraSPARC-IIi-based system.

The APB provides the UltraSPARC-IIi microprocessor direct access, with minimum latency, to devices located on a connected PCI bus and mapped in the processor’s I/O or memory address space. In addition, it provides PCI masters direct, high-capacity access to main memory. Use of the APB depends upon the organization of the PCI bus.

Features

  • 32-Bit PCI Revision 2.1 Compatible [1]
  • PCI Bridge Specification 1.0 Compatible [1]
  • 32-Bit Memory Addressing for PIO and DMA
  • 64-Bit Memory Addressing (DACs) for DMA
  • 24-Bit I/O Addressing (PIO only)
  • Full Concurrency for Primary and Secondary PCI Interfaces
    • Uses Deadlock Detection / Recovery Mechanism
  • Data Buffering
    • A 72-Byte Buffer (FIFO) on each of the DMA and PIO Paths
  • Two On-Chip Programmable Arbiters
    • One for each Secondary PCI Interface
    • Each One Handles up to 4 Secondary Bus Masters
    • Priority to each Master is Programmable, so any Master can be Given Priority
  • External Arbiters for Secondary PCI Buses Allowed
  • Retry Counters and Latency Timers can be Configured for Differing Performance Requirements
  • Prefetching for some Memory Read Commands
  • Prefetching Algorithm can be Varied for DMA
  • Interrupt Handling
    • Synchronization Mechanism for DMA Writes
    • PCI Interrupts are Routed through an External Interrupt Concentrator
  • PCI Optional Features Implemented [2]
    • Fast Back-to-Back Capable as a Target
    • Medium Decode Timing
  • Boot Mode Allows APB to Be Used in the Path of the Boot PROM
  • Transactions Originating on One Secondary Bus Cannot Be Destined for Targets on the Other
  • Little-Endian to the Bus and Internal Configuration Space
  • Errors Resulting in Assertion of SERR# Are Logged
  • PIO Reads and Writes are in Non-Cacheable Memory Space (When Used with UltraSPARC-IIi)
Last updated 2019-04-30T00:00:00Z

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