82309 Address Bus Controller Overview

The 82309 Address Bus Controller provides Address decoding for devices on the motherboard, including the shadowed DRAM address of the ROM BIOS. The Address Bus Controller also has Integrated· DRAM controller, Refresh Timer and miscellaneous registers for memory control and error recovery, specifically ports EO, E1, E3, E4, E5, E7 and 103.

The 82309 Address Bus Controller provides the designer several price/performance choices for the configuration of up to 16 MBytes of Page Interleave DRAM memory on the motherboard. Up to four banks of 256K, 1M and 4M DRAMs are supported.

The 82309 Address Bus Controller generates periodic refresh requests to the 82307 DMA controller to run refresh cycles. The 82309 does not use the Refresh Address generated by the DMA controller but provides its own refresh address to the 256K, 1M and 4M DRAMs.

82309 Features

• Address Decoder
• DRAM Controller ... Up to Four Banks of Page Interleaved Memory (Max 16M) Refresh Timer
• Integrated I/O Ports and Registers
• Low Power CHMOS Technology
• 100Pin Plastic Quad Flat Packaging

(See Packaging Spec., Order # 231369)