82EC495 System Controller (SYSC)

SYSC monitors two reset sources, RSTl## and RST2#, and generates CPURST and NPRST signals to CPU and coprocessor, respectively. The SYSC Controller contains Burst Line Fill Control Logic. The controller provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock Generation for CPU Processor and AT-Bus, two Noncacheable Address Comparators, CPU Interface Control, Integrated Write-back Cache Controller with Built-in Tag Comparator, Decoupling Refresh for Local DRAM and AT-Bus Memory.