Description:

AMD-751

The AMD-751 System Controller is a critical component of the AMD-750 chipset, designed to provide enhanced performance for systems powered by the AMD Athlon processor and other compatible processors. This controller integrates several key features and functionalities:

1. AMD Athlon System Bus:

   • Utilizes a high-performance point-to-point system bus topology.
   • Employs source-synchronous clocking for high-speed data transfers.
   • Adopts HSTL-like low-voltage swing transceiver logic signal levels.
   • Features three independent high-speed channels, including a processor request channel, a system probe channel, and a data transfer channel.
   • Achieves peak data transfer rates of 1.6 gigabytes per second at 200 MHz.
   • Supports large 64-byte data burst transfers.
   • Implements various data buffers, including memory write and read FIFOs and PCI/APCI write and read buffers.
   • Utilizes transaction queues such as command queue (CQ), memory write queue (MWQ), memory read queue (MRQ), and probe (snoop) queue (PQ).

2. Integrated Memory Controller:

   • Includes a Memory Request Organizer (MRO) that optimizes scheduling of memory requests.
   • Supports various concurrences, including processor-to-main-memory with PCI-to-main-memory and AGP-to-main-memory.
   • Provides memory error correcting code (ECC) support.
   • Supports up to three non-buffered PC-100 Rev. 1.0 SDRAM DIMMs with flexible row and column addressing.
   • Allows for up to 768 megabytes of memory.
   • Features four open pages within one CS (chip select) for one quadword and supports a default two-page leapfrog policy for eight quadword requests.

3. PCI Bus Controller:

   • Complies with the PCI Local Bus Specification, Revision 2.2.
   • Supports up to six PCI masters.
   • Utilizes a 32-bit interface compatible with both 3.3-V and 5-V PCI I/O.
   • Operates synchronously up to 33 MHz.
   • Features automatic processor-to-PCI burst cycle detection.
   • Includes FIFOs to enhance performance, with zero wait-state PCI initiator and target burst transfers.
   • Supports various PCI command optimizations.
   • Ensures fair arbitration between PCI initiators using timers.
   • Allows for retry disconnect to improve bus utilization.

4. AGP Features:

   • Complies with AGP 2.0 specification.
   • Supports synchronous 66-MHz 1x and 2x data-transfer modes.
   • Utilizes separate read-request and write-request queues.
   • Implements reordering of high-priority requests.
   • Includes transaction queues for memory-to-AGP and processor-to-AGP operations.
   • Features FIFOs for AGP-to-memory write and memory-to-AGP read operations.
   • Utilizes a conventional GART (graphics address remapping table) scheme with associated caches.

5. Power Management:

   • Supports power management compliance for both ACPI and Microsoft PC 98 power management standards.
   • Provides support for various power states, including Processor Halt/Stop Grant/Sleep states and Power-On Suspend.